Architecture Is Elementary Revised

Architecture is Elementary, Revised

Awarded for its unique ink illustrations, this newly revised edition of Architecture is Elementary is a self-instruction book that concisely and coherently discusses the principles of architectural design. Stimulating lessons challenge the lay person and trigger creative responses. New features include a fresh design and layout, 50 new illustrations of recent and planned buildings, and new lessons that update the book for the world of twenty-first-century architecture. Author Nathan Winters explains the rationale for developers choosing to build higher and taller with modern high-rises, and explores the engineering challenges for such giant structures. He also addresses the dangers of such adventurous design in this century, including becoming tempting targets for terrorists. Architecture is Elementary also explores issues surrounding modern landscape architecture, as Winters looks at the impact of green design and cities that seek to reclaim useless spaces (such as inactive railroad lines), converting them into parks for urban use. He also explores the financial and economic benefits of beautified landscape. The new layout, new lesson materials, and current examples of future thinking in the world of architecture make this a must-have for every serious teacher, student, and practitioner of architecture.

An Encyclopædia of Architecture ... Revised, with Alterations and Considerable Additions by W. Papworth. New Edition

VLSI Architectures for Modern Error-Correcting Codes

Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI Architectures for Modern Error-Correcting Codes serves as a bridge connecting advancements in coding theory to practical hardware implementations. Instead of focusing on circuit-level design techniques, the book highlights integrated algorithmic and architectural transformations that lead to great improvements on throughput, silicon area requirement, and/or power consumption in the hardware implementation. The goal of this book is to provide a comprehensive and systematic review of available techniques and architectures, so that they can be easily followed by system and hardware designers to develop en/decoder implementations that meet error-correcting performance and cost requirements. This book can be also used as a reference for graduate-level courses on VLSI design and error-correcting coding. Particular emphases are placed on hard- and soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary and non-binary low-density parity-check (LDPC) codes. These codes are among the best candidates for modern and emerging applications due to their good error-correcting performance and lower implementation complexity compared to other codes. To help explain the computations and en/decoder architectures, many examples and case studies are included. More importantly, discussions are provided on the advantages and drawbacks of different implementation approaches and architectures.