Analysis Of Cache Performance In Vector Processors And Multiprocessors

Analysis of Cache Performance in Vector Processors and Multiprocessors

Analysis of Cache Performance for Operating Systems and Multiprogramming

As we continue to build faster and fast. er computers, their performance is be coming increasingly dependent on the memory hierarchy. Both the clock speed of the machine and its throughput per clock depend heavily on the memory hierarchy. The time to complet. e a cache acce88 is oft. en the factor that det. er mines the cycle time. The effectiveness of the hierarchy in keeping the average cost of a reference down has a major impact on how close the sustained per formance is to the peak performance. Small changes in the performance of the memory hierarchy cause large changes in overall system performance. The strong growth of ruse machines, whose performance is more tightly coupled to the memory hierarchy, has created increasing demand for high performance memory systems. This trend is likely to accelerate: the improvements in main memory performance will be small compared to the improvements in processor performance. This difference will lead to an increasing gap between prOCe880r cycle time and main memory acce. time. This gap must be closed by improving the memory hierarchy. Computer architects have attacked this gap by designing machines with cache sizes an order of magnitude larger than those appearing five years ago. Microproce880r-based RISe systems now have caches that rival the size of those in mainframes and supercomputers.

The Cache Coherence Problem in Shared-Memory Multiprocessors

Almost all software solutions are developed through academic research and implemented only in prototype machines leaving the field of software techniques for maintaining the cache coherence widely open for future research and development. This book is a collection of all the representative approaches to software coherence maintenance including a number of related efforts in the performance evaluation field. The book presents a selection of 27 papers dealing with state-of-the-art software solutions for cache coherence maintenance in shared-memory multiprocessors. It begins with a set of four introductory readings that provides a brief overview of the cache coherence problem and introduces software solutions to the problem. The text defines and illustrates static and dynamic software schemes, techniques for modeling performance evaluation mechanisms, and performance evaluation studies. The book is intended for the experienced reader in computer engineering but possibly a novice in the topic of cache coherence. It also provides an in-depth understanding of the problem as well as a comprehensive overview for multicomputer designers, computer architects, and compiler writers. In addition, it is a software coherence reference handbook for advanced undergraduate and typical graduate students in multiprocessing and multiprogramming areas.