Advanced Gate Technologies For Deep Submicron Cmosfets

Advanced Gate Technologies for Deep-submicron CMOSFETs

Low-Power Deep Sub-Micron CMOS Logic

1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as "Moore's Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase.In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa gation delay, which results in a lower data-processing speed performance.

ESD Protection Device and Circuit Design for Advanced CMOS Technologies

ESD Protection Device and Circuit Design for Advanced CMOS Technologies is intended for practicing engineers working in the areas of circuit design, VLSI reliability and testing domains. As the problems associated with ESD failures and yield losses become significant in the modern semiconductor industry, the demand for graduates with a basic knowledge of ESD is also increasing. Today, there is a significant demand to educate the circuits design and reliability teams on ESD issues. This book makes an attempt to address the ESD design and implementation in a systematic manner. A design procedure involving device simulators as well as circuit simulator is employed to optimize device and circuit parameters for optimal ESD as well as circuit performance. This methodology, described in ESD Protection Device and Circuit Design for Advanced CMOS Technologies has resulted in several successful ESD circuit design with excellent silicon results and demonstrates its strengths.