Accelerating Secure Computations Under Fully Homomorphic Encryption


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Accelerating Secure Computations Under Fully Homomorphic Encryption


Accelerating Secure Computations Under Fully Homomorphic Encryption

Author: Alhassan Khedr

language: en

Publisher:

Release Date: 2017


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Fully homomorphic encryption (FHE) systems enable computations on encrypted data without decrypting and without knowledge of the secret key. In this thesis, we describe an optimized RLWE-based and NTRU-based variants of the FHE system recently proposed by Gentry, Sahai and Waters (GSW). Although the GSW system was widely believed to be less efficient than its contemporaries due to the dimensionality of its ciphertext, we demonstrate quite the opposite behavior. We first highlight and carefully exploit the algebraic features of the system to achieve significant speedup over the state-of-the-art FHE implementations, namely the IBM homomorphic encryption library (HElib) and DARPA's SIPHER implementation. We introduce several optimizations on top of our HE implementation, and use the resulting scheme to construct numerous secure applications. We introduce the first high performance Homomorphic Processing Unit (HPU) hardware accelerator. A carefully crafted parallel GPU implementation of our RLWE scheme running on an NVIDIA GeForce GTX980 achieved a speedup factor of 89,700x compared to DARPA's SIPHER v01 baseline implementation. Our single-staged homomorphic processing unit (HPU) hardware accelerator achieved a speedup factor of 57x compared to our GPU implementation. Our NTRU scheme is mathematically 4x more efficient than our RLWE scheme. In total, our NTRU scheme running on one single-staged HPU unit managed to achieve a combined speedup factor of 2x10^7 compared to DARPA's SIPHER v01 baseline implementation, which is twice the performance target originally set by DARPA's PROCEED program to accelerate fully homomorphic encryption. An additional 4.47x speedup can be achieved by implementing a log(n)-staged HPU unit at the cost of 3x the die area. Finally, by exploiting the computational independence in our FHE schemes and applications, a speedup factor of 10^9 can be achieved by distributing independent computations on 50 single-staged HPU units.

XeHE: an Intel GPU Accelerated Fully Homomorphic Encryption Library: A SYCL Sparkler: Making the Most of C++ and SYCL


XeHE: an Intel GPU Accelerated Fully Homomorphic Encryption Library: A SYCL Sparkler: Making the Most of C++ and SYCL

Author: Alexander Lyashevsky

language: en

Publisher: James Reinders

Release Date: 2023-04-02


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This installment of a "SYCL Sparkler" explores in depth a way to implement a reasonably efficient implementation for Homomorphic Encryption using modern C++ with SYCL. As a result of their work, the authors learned some valuable optimization techniques and insights that the they have taken time to share in this very interesting and detailed piece. A key value of using C++ with SYCL, is the ability to be portable while supporting the ability to optimize at a lower level when it is deemed worth the effort. This work helps illustrate how the authors isolated that optimization work, and their thought process on how to pick what to optimize. The code for this implementation is available open source online. None of the performance numbers shown are intended to provide guidance on hardware selection. The authors offer their results and observations to illustrate the magnitude of changes that may correspond to the optimizations being discussed. Readers will find the information valuable to motivate their own optimization work on their applications using some of the techniques highlighted by these authors. Key Insights shared include: pros/cons of a hand-tuned vISA, memory allocation overheads, multi-tile scaling, event-based profiling, algorithm tuning, measuring of device throughput, developing with 'dualities' to increase portability and performance portability.

Security of FPGA-Accelerated Cloud Computing Environments


Security of FPGA-Accelerated Cloud Computing Environments

Author: Jakub Szefer

language: en

Publisher: Springer Nature

Release Date: 2023-12-28


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This book addresses security of FPGA-accelerated cloud computing environments. It presents a comprehensive review of the state-of-the-art in security threats as well as defenses. The book further presents design principles to help in the evaluation and designs of cloud-based FPGA deployments which are secure from information leaks and potential attacks.