A Performance Driven Placement System Using An Integrated Timing Analysis Engine
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A Performance Driven Placement System Using an Integrated Timing Analysis Engine
With the increase in design sizes the physical design of VLSI circuits continues to become more challenging. Achieving timing closure on such large designs with tight timing, area, power and design rule constraints is a difficult task. It is therefore important to come up with a placement which addresses these constraints to a good extent in order to facilitate timing closure. Popular placement algorithms like analytic placement rely on total wire length as a metric to optimize placement. But total wire length is not an accurate measure of critical path delay and the resulting placement may not meet timing requirements. Timing driven placers try to address this issue by incorporating a more complex metric that takes into account the timing requirements. But most of these approaches are either restricted to detailed placement or the timing information supplied is not sufficient or accurate enough. In this work we come up with a timing driven placement system that incorporates a relatively fast and accurate incremental timing engine with a placement engine. We show that starting with an unplaced netlist, using the information from the timer, we can produce placements which give better timing results post routing compared to wire length based placement. Although it is at a cost of some runtime, the better post routing results could give an overall better turnaround time as the number of iterations through the physical design flow could be reduced.
Handbook of Algorithms for Physical Design Automation
The physical design flow of any project depends upon the size of the design, the technology, the number of designers, the clock frequency, and the time to do the design. As technology advances and design-styles change, physical design flows are constantly reinvented as traditional phases are removed and new ones are added to accommodate changes in
Multi-Objective Optimization in Physical Synthesis of Integrated Circuits
Author: David A. Papa
language: en
Publisher: Springer Science & Business Media
Release Date: 2012-08-09
This book introduces techniques that advance the capabilities and strength of modern software tools for physical synthesis, with the ultimate goal to improve the quality of leading-edge semiconductor products. It provides a comprehensive introduction to physical synthesis and takes the reader methodically from first principles through state-of-the-art optimizations used in cutting edge industrial tools. It explains how to integrate chip optimizations in novel ways to create powerful circuit transformations that help satisfy performance requirements.