A Hardware Implementation Of Vhash A Universal Hashing Algorithm Using System Verilog
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A Hardware Implementation of VHASH, a Universal Hashing Algorithm Using System Verilog
Hacking and Phishing are major threats in today's informational world. Information security is a major concern for Information Technology (IT) specialists. Hackers and other untrusted parties try to access the confidential information using different hacking schemes. The only stable and long-term solution to security threats is enforcing a strong and complex method of identity assurance. To achieve this, IT specialists incorporate different encryption techniques. In general, encryption refers to transforming the information into ciphered text using ciphers (algorithms). The ciphered text is readable, and only authenticated parties can decipher it. Hence, encryption is one of the major security solutions. Encryption involves a number of algorithms, one of which is cryptographic hashing. To enhance the performance of software algorithms, the developers rely on hardware accelerators. A hardware accelerator is a specific hardware unit apart from the CPU that performs a dedicated software or algorithmic implementation. In this project, a hardware implementation of a hashing algorithm known as VHASH is proposed. It was designed for exceptional performance on the systems that support 64-bit multiplication efficiently [5]. The hardware implementation of the VHASH algorithm involved modeling the algorithm in System Verilog hardware description language, validating and synthesizing it using a current hardware cell library. The testbench developed for verifying the design used System Verilog Functional Coverage to make sure the design was thoroughly verified. Verification was performed on Synopsys VCS® tool. The expected results used in validating the implementation were generated based on an existing python code for VMAC from [3]. The final phase of the project involved synthesizing the System Verilog model of VHASH algorithm towards LSI_10k technology library.
CAD for Hardware Security
Author: Farimah Farahmandi
language: en
Publisher: Springer Nature
Release Date: 2023-05-11
This book provides an overview of current hardware security problems and highlights how these issues can be efficiently addressed using computer-aided design (CAD) tools. Authors are from CAD developers, IP developers, SOC designers as well as SoC verification experts. Readers will gain a comprehensive understanding of SoC security vulnerabilities and how to overcome them, through an efficient combination of proactive countermeasures and a wide variety of CAD solutions.
Versatile Hardware Analysis Techniques
This book describes several versatile hardware analysis techniques that tackle existing and new challenges. These techniques cover different phases of the hardware development process, including the verification, debugging, and post-synthesis optimization phases. The authors introduce the Waveform Analysis Language (WAL), which allows users to code analysis tasks in the form of programs that run on waveforms. The book covers processor verification, formal microcode verification, programmable automated waveform analysis demonstrated for a large variety of previously manual analysis tasks, as well as netlist optimization leveraging formal methods. All methods are available as open source, typically include examples on RISC-V analysis problems, providing a strong foundation for the community.