17th Ieee Vlsi Test Symposium
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17th IEEE VLSI Test Symposium
Author:
language: en
Publisher: Institute of Electrical & Electronics Engineers(IEEE)
Release Date: 1999
The theme of the April 1999 symposium Scaling deeper to submicron: test technology challenges reflects the issues being created by the move toward nanometer technologies. Many creative and novel ideas and approaches to the current and future electronic circuit testing-related problems are explored
19th IEEE VLSI Test Symposium
Author:
language: en
Publisher: Institute of Electrical & Electronics Engineers(IEEE)
Release Date: 2001
Collects 58 papers from the April/May 2001 symposium that explore new approaches in the testing of electronic circuits and systems. Key areas in testing are discussed, such as BIST, analog measurement, fault tolerance, diagnosis methods, scan chain design, memory test and diagnosis, and test data compression and compaction. Also on the program are sessions on emerging areas that are gaining prominence, including low power testing, testing high speed circuits on low cost testers, processor based self test techniques, and core- based system-on-chip testing. Some of the topics are robust and low cost BIST architectures for sequential fault testing in datapath multipliers, a method for measuring the cycle-to-cycle period jitter of high-frequency clock signals, fault equivalence identification using redundancy information and static and dynamic extraction, and test scheduling for minimal energy consumption under power constraints. No subject index. c. Book News Inc.